This invention generally relates to a fault location or diagnosis technique useful in logic IC devices.
When a fault has occurred in actual products of, for example, logic VLSI (Very Large Scale Integration) devices, a fault diagnosis for locating the fault and investigating the cause thereof is essential for improving the quality and performance of the products.
Conventionally, as for such a fault diagnosis technique for logic VLSI devices, there is known a logic VLSI test technique which prints out, when a function of a logic VLSI device is faulty, the position of a test pattern representing a fault, an output pattern from the logic VLSI device, contents of the fault, and so on.
Incidentally, in a fault simulation for a fault location of a semiconductor device such as a logic VLSI device having a plurality of logic stages, a so-called hazard may occur, in which an undeterminable logical signal pattern which can be logically regarded as either "1" or "0", is generated due to racing of logical output signals in preceding stages, and such an undeterminable state propagates up to an output pin. The occurrence of hazard causes the test result of a device to be indefinite, and therefore the conventional technique fails to precisely locate a fault. An example of such semiconductor device may be a logic VLSI device including a sequential circuit.
An example of a problem on a fault location caused by hazard will hereinbelow be described specifically.
In a fault location technique for logic VLSI devices including a fault simulation, when the fault simulation is executed, a racing of logical states among respective signals causes a hazard in a flip-flop (for example, an RS flip-flop) in which a logical state becomes undeterminable, whereby the flip-flop is supposed to generate an output "X" (unknown) which is different from either of "1" and "0". For this reason, if this hazard has occurred on a bus on which a fault Z (for example, a degenerate fault at a single location) propagates, the fault Z cannot be detected by a test.
On the other hand, in a test of faulty logic VLSI device chips, input pins of a device chip are collectively supplied with a plurality of digital input signals forming an input pattern, and logical levels ("1" or "0") of a plurality of digital output signals derived at output pins at this time are matched or collated with expected values or levels of the device chip produced by a simulation performed with a fault-free logic ("1", "0" or "X"), and a chip under test is determined as fault-free ("DON'T CARE" determination) whenever an expected value is undeterminable ("X") due to an occurrence of a hazard.
Therefore, when the result of a fault simulation is matched with the test result of a faulty logic VLSI device, the above-mentioned hazard causes a problem that both results are not always coincident, which results in failing to locate a fault.
JP-A-3-120485 (laid open on May 22, 1991) shows an efficient fault location using a virtual gate. However, this publication does not discuss bad influences of the hazard on the fault location.